Low-complexity Algorithm for Arrhythmia Detection

Github| Project Page

Group: Sashini Liyanage, Isuri Devindi

A pre-packaged software solution containing a set of low-complexity algorithms for QRS-peak detection and ECG signal compression addressing the null-power consumption environments, along with a Spiking Neural Network implementation to classify ECG beats based on arrhythmia conditions.

• Methods: Signal filtering, Leaky-boundary based QRS-peak detection, Quantization, Spiking Neural Networks

Oral Cancer Prediction System from White Light Images

Poster | Youtube

Group: Sashini Liyanage, Achintha Harshamal, Isuri Devindi, Dinura Dissanayake

A web-based tool to reduce the delay in diagnosing high-risk oral cancer patients by incorporating an automated oral cancer prediction model trained on a white light image database derived from the Sri Lankan population.

• Technologies: DenseNet and an XGBoost classifier, React.js, Express.js, flask framework
• Contribution: Development of a web-based annotation tool and Development of the ensemble machine learning model to predict oral cancer using multiple data sources such as images and risk factors.

Reconstructing highly degraded license plates

Report

Group: Sashini Liyanage, Aminda Amarasinghe, Isuri Devindi, N. Varnaraj

A procedure to extract a number plate from an image and reduce several noises due to low resolution, high or low lighting, and motion blur to reconstruct highly degraded images of license plates.

• Technologies: Python, OpenCV, EasyOCR
• Techniques: Morphological transformation, Contouring, Spatial, and Frequency domain filtering

Remote Proctoring Device

Github | Project Page

Group: Sashini Liyanage, Isuri Devindi, Savindu Wannigama

A single device that integrates the hardware and software components needed to conduct an examination in online mode with no technical interruption.

• Technologies: ReactJS, ElectronJs, Nodejs, MongoDB, Rest API, AWS
• Contribution: Desktop app development, Hardware design

8-bit single cycle processor

Github

Group: Sashini Liyanage, Madhushan Ramalingam

Implement a simple 8-bit single-cycle processor which includes a CPU with a data memory unit and data cache using Verilog HDL

• Technologies: Verilog-HDL